Looking
back to the circuit in Figure 30, we see that
the last rank of full adder gates are also hysteresis
gates that maintain their state between wave fronts
just like the asynchronous register gates.
Since the wave front state is maintained by the
adder gates there is really no need for a separate
rank of gates just to maintain state (i.e.,
a separate asynchronous register). We can
connect the acknowledge line directly to the last
rank of processing gates and integrate the asynchronous
registration function directly into the combinational
circuit as shown in Figure 32.
With both input meanings and the acknowledge control
signal going into the last rank of gates their
threshold must now be 4.
Figure 32. Ripple carry adder with embedded
asynchronous register.
NULL Convention Logic expresses data processing
and control identically and indeed the expressional
distinction between the two domains disappears.
NULL Convention Logic is a uniform, consistent
and general language for the expression of asynchronous
circuits and systems. NCL delivers on the promises
of asynchronous design where the traditional Boolean
logic based approaches have failed to deliver. |
