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The registers and circuits can be configured in more complex structures than a simple pipeline. Figure 23 shows a fan-in configuration of circuits.

Figure 23

Figure 23. Fan-in configuration of registers and circuits.

In Figure 23 each threshold 2 gate represents a complete rank of register gates. In this configuration three circuits present their results to a single circuit. The single circuit receives the wave fronts from all three and does not signal completeness of DATA or completeness of NULL until all three wave fronts are present and complete. It then sends the acknowledge to all three. The wave fronts of the three circuits are synchronized at the register of the single circuit.

Figure 24

Figure 24. Fan-out configuration of registers and circuits.

Figure 24 shows a fan-out configuration where a single circuit delivers its result values to three circuits. Each of the three circuits receives the wave front individually and generates its own acknowledge control signal. The threshold three gate collects the acknowledge signals. It does not assert DATA until all three acknowledge inputs are DATA, meaning all three circuits have received a complete DATA wave front, and it does not assert NULL until all three acknowledge inputs are NULL, meaning that all three have received a complete NULL wave front. So the fanned-out wave front is synchronized by the threshold 3 gate.

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