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Asynchronous Register Summary

The asynchronous register manages the fully asynchronous flow of data wave fronts and NULL wave fronts among NULL Convention Logic circuits. Passage of DATA or NULL through a register occurs strictly after the request for DATA or NULL, and the detection of complete DATA or all NULL state occurs strictly after the passage and storage of the DATA or NULL values. The asynchronous registers and their behavior are fully delay insensitive and are purely symbolically determined. There are no time dependency relationships whatever. With the asynchronous register a fully delay insensitive and purely symbolically determined system can be built.

Structures of Asynchronous Registers

The interaction behavior among combinational circuits can be seen with the simple pipeline example shown in Figure 22.

Figure 22

Figure 22. NULL Convention asynchronous pipeline.

Assume that all the circuits are in a NULL state and that the current watcher and the next watcher is requesting a DATA wave front and that the previous register is presenting a complete DATA set to its combinational circuit. As the wave front propagates through the previous circuit to the current register, the current register passes the data since its control line is DATA. When a complete data set is recognized by the current watcher, the current watcher transitions its control line to the previous register to NULL to indicate that it has received and stored the data wave front and the previous register can pass a NULL wave front. The requested NULL wave front from the previous register can arrive at the current register but, as long as its control line is DATA, the NULL wave front will be blocked and the current register will maintain the presentation of the set of DATA values to the current circuit. The control line for the current register will remain DATA until the DATA wave front has propagated through the current circuit and has been received by the next register. When the next register receives and stores the DATA wave front, the DATA set no longer needs to be maintained by the current register. The next watcher detects the complete DATA set and transitions its acknowledge line to NULL to indicate that it has the DATA wave front and the current register can allow a NULL wave front through.

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