Some Adder Circuits
Next we show some adder circuits to demonstrate
some advantages of NCL over previous approaches
to asynchronous circuits. To give a sense of the
logic we begin with the Boolean logic Minterm
form of the full adder shown in Figure 26.
Figure 26. Minterm version of full adder.
This can be transformed directly into an asynchronous
delay insensitive circuit by replacing the AND
gates with 3 input C-elements as shown in Figure
27. This is a well known asynchronous circuit
called delay insensitive minterm synthesis or
DIMS . What
is not known is how to optimize this circuit which
is expressed partly in Boolean logic and partly
in terms of C-elements.
Figure 27. Minterm version of full adder.