Theseus Research : Technical Papers : NULL Convention Logic™ Page 13 of 26

Figure 15. Translating between intermediate encoded gates and hysteresis gates.

As can be seen Intermediate encoding is very expensive in terms of resources. The wires are all doubled and each encoded gate is several simple threshold gates. The feedback solution is more practical and economical.

Now that both forms of NULL Convention threshold gates enforce the completeness of input criteria for both DATA in relation to NULL and for NULL in relation to DATA, their behavior again scales up for circuits as a whole. Figure 16 shows the data-NULL cycle for a single data value NULL Convention Logic circuit.

Figure 16. NULL-DATA cycle for hysteresis gate circuit.

Beginning with the circuit in an all NULL state one DATA value is applied in one of the groups. The result values remain all NULL since no threshold is met. When a DATA value is applied in the second group, a complete input data set is present, the threshold of a gate is met which asserts a DATA value which propagates to the result values. One result value in each output group asserts a DATA value which constitutes a complete result data set and expresses the correct resolution of a complete input data set. The circuit as a whole enforces the completeness of input criteria for DATA in relation to NULL and only asserts a complete result data set when a complete input data set is presented to the circuit.

One of the input DATA values becomes NULL, but the threshold 2 gate and the circuit continue asserting DATA result values. Only when all inputs to the circuit are NULL does the threshold 2 gate and hence the circuit transition their result values to NULL. The circuit as a whole enforces the completeness of input criteria for NULL in relation to DATA and only asserts all NULL result values when the input to the circuit is all NULL and the NULL values have propagated through the circuit.

As with the Boolean logic examples with three and four value logic, the completion of resolution of a complete input data set and the readiness of the circuit to receive a new input data set to resolve can be determined by simply monitoring the result values. The circuit is symbolically complete and manages quite on its own its interactions with the rest of the world.