The
Encoded Intermediate Value Solution
Since we are limited to two values in the most
primitive mutually exclusive value assertion domain
we can't just add another value as we did in the
Boolean logic example, so we have to encode another
value. The intermediate value solution involves
another level of encoding convention on top of
the mutually exclusive assertion group encoding.
As things stand so far, each data meaning is expressed
with one data value on one wire. True is one wire
and False is another wire. Now we will express
each data meaning with two wires. True will be
expressed with two wires and False will be expressed
with two wires. encoded_DATA, encoded_INTERMEDIATE
and encoded_NULL are expressed on these two wires
with the following encoding.
DATA, DATA -> encoded_DATA
DATA, NULL -> encoded_INTERMEDIATE
NULL, DATA -> encoded_INTERMEDIATE
NULL, NULL -> encoded_NULL
As shown in Figure 12, each input to a gate is
two wires and a single intermediate value gate
consists of several threshold gates without hysteresis.
Figure 12. Intermediate encoded 2 input threshold
2 gate.
Starting with the intermediate value gate in an
all NULL state with encoded_NULL values on the
inputs and asserting an encoded_NULL value. If
one DATA value is applied to A_1 the threshold
1 gate meets its threshold and will assert a DATA
result value and the result value for the composite
gate will assert DATA, NULL to express the encoded_INTERMEDIATE
value. The result value remains encoded_INTERMEDIATE
until all four input wires are DATA, which means
that both inputs are presenting encoded_DATA values
and there is a complete input data set, at which
time the threshold 4 gate asserts a DATA value
and the intermediate value gate asserts DATA,
DATA to express the encoded_DATA value. As soon
as one input wire becomes NULL the threshold 4
gate falls below its threshold and asserts NULL
and the asserted result for the intermediate value
gate is DATA, NULL expressing the encoded_INTERMEDIATE
value. The encoded_INTERMEDIATE value is maintained
until all the input wires become NULL at which
time the threshold 1 gate asserts a NULL value
and the result value for the composite gate is
NULL, NULL expressing the encoded_NULL value. |